aidanbrzezinski/Nixie_Tube_Clock
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Nixie Tube Clock

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Blocked

Bug/Issue

CHECKED

dev

DRAFT

ERC/DRC

HV

In Review

Manufacturing

master

PCB Layout

PRELIMINARY

Quick Win

RELEASED

Research

Schematic

Assignee
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aidanbrzezinski
30
Backlog
Sheet 1 - Cover Page and Title Block
#16 opened 2026-03-16 21:53:23 -05:00 by aidanbrzezinski
DRAFT
DRAFT Schematic
Sheet 2 - Block Diagram
#17 opened 2026-03-16 21:53:26 -05:00 by aidanbrzezinski
DRAFT
DRAFT Schematic
Sheet 4 - Power - HV Boost
#19 opened 2026-03-16 21:54:17 -05:00 by aidanbrzezinski
DRAFT
DRAFT HV Schematic
Sheet 5 - Power - Logic Supply
#20 opened 2026-03-16 21:54:41 -05:00 by aidanbrzezinski
DRAFT
DRAFT Schematic
Sheet 7 - MUX Inputs - Time Logic
#22 opened 2026-03-16 21:55:55 -05:00 by aidanbrzezinski
DRAFT
DRAFT Schematic
Sheet 8 - MUX Inputs - Date Logic
#23 opened 2026-03-16 21:56:04 -05:00 by aidanbrzezinski
DRAFT
DRAFT Schematic
Sheet 11 - Switching MUX
#26 opened 2026-03-16 21:56:18 -05:00 by aidanbrzezinski
DRAFT
DRAFT Schematic
Sheet 6 - Clock - Crystal Oscillator and Divider
#21 opened 2026-03-16 21:55:08 -05:00 by aidanbrzezinski
DRAFT
DRAFT Schematic
Sheet 19 - PWM Dimming
#34 opened 2026-03-16 21:57:07 -05:00 by aidanbrzezinski
DRAFT
DRAFT HV Schematic
Sheet 9 - MUX Inputs - Anti-Poisoning Logic
#24 opened 2026-03-16 21:56:07 -05:00 by aidanbrzezinski
DRAFT
DRAFT Schematic
Sheet 16 - Counter Based Sequencer
#31 opened 2026-03-16 21:56:54 -05:00 by aidanbrzezinski
DRAFT
DRAFT Schematic
Sheet 14 - BCD Latch and Serializing
#29 opened 2026-03-16 21:56:46 -05:00 by aidanbrzezinski
DRAFT
DRAFT Schematic
Sheet 10 - MUX Selection Logic
#25 opened 2026-03-16 21:56:12 -05:00 by aidanbrzezinski
DRAFT
DRAFT Schematic
Sheet 12 - User Inputs
#27 opened 2026-03-16 21:56:26 -05:00 by aidanbrzezinski
DRAFT
DRAFT Schematic
Sheet 18 - Nixie Tubes
#33 opened 2026-03-16 21:57:02 -05:00 by aidanbrzezinski
DRAFT
DRAFT HV Schematic
Sheet 13 - Increment Decrement Selection Logic
#28 opened 2026-03-16 21:56:32 -05:00 by aidanbrzezinski
DRAFT
DRAFT Schematic
Sheet 15 - BCD to One-Hot Decoder
#30 opened 2026-03-16 21:56:49 -05:00 by aidanbrzezinski
DRAFT
DRAFT Schematic
Sheet 17 - Nixie Driver
#32 opened 2026-03-16 21:56:57 -05:00 by aidanbrzezinski
DRAFT
DRAFT HV Schematic
Verify KiBot DRAFT variant runs cleanly
#35 opened 2026-03-16 21:57:18 -05:00 by aidanbrzezinski
DRAFT
dev DRAFT
Source IN-8 tube pin sockets
#4 opened 2026-03-16 21:42:41 -05:00 by aidanbrzezinski
Research & Planning
HV Research
Finalize custom footprints
#12 opened 2026-03-16 21:50:49 -05:00 by aidanbrzezinski
Research & Planning
Research Schematic
Confirm NCH6300HV output voltage setting
#7 opened 2026-03-16 21:43:04 -05:00 by aidanbrzezinski
Research & Planning
HV Research
Decide colon separator - Nixie neon bulb or dot indicators
#5 opened 2026-03-16 21:42:48 -05:00 by aidanbrzezinski
Research & Planning
HV Research
Verify SN74HC153DR for 3-to-1 MUX
#10 opened 2026-03-16 21:47:33 -05:00 by aidanbrzezinski
Research & Planning
Research Schematic
Confirm IN-8 sustain voltage and cathode resistor value
#6 opened 2026-03-16 21:42:53 -05:00 by aidanbrzezinski
Research & Planning
HV Research
Decide PWM dimming implementation
#8 opened 2026-03-16 21:44:51 -05:00 by aidanbrzezinski
Research & Planning
Research
Decide AP cycle timer interval and trigger
#9 opened 2026-03-16 21:45:39 -05:00 by aidanbrzezinski
Research & Planning
Research
Finish creating symbols in KiCad library
#11 opened 2026-03-16 21:50:12 -05:00 by aidanbrzezinski
Research & Planning
Research Schematic
Define KiCad net classes for HV vs logic
#13 opened 2026-03-16 21:51:02 -05:00 by aidanbrzezinski
Research & Planning
HV PCB Layout Research
Define input voltage range and target specifications
#14 opened 2026-03-16 21:51:14 -05:00 by aidanbrzezinski
Research & Planning
Research
4
In Progress
0
Research & Planning
0
DRAFT
0
PRELIMINARY
0
CHECKED
0
RELEASED
0
Manufacturing & Bring-up
0
Complete